1.1. Field of the Invention
The present invention relates to the field of computer main memory control, and in particular to method for operating a DRAM main memory.
1.2. Description and Disadvantages of Prior Art
Dynamic RAM (DRAM) units are currently the prevailing implementation of (main) memory chips, as this memory type is quite cheap and its use has become more and more extensive in the last two decades of processor development, since their great advantage is the high spatial storage density, as only one transistor is needed in a memory cell for storing a single bit. DRAM is usually organized in logical subdivisions called memory pages. A memory page has a physical structure similar to a 2-dimensional table including columns and rows of storage locations. A memory page may contain for example one Megabyte of storage capacity.
Disadvantageously, DRAM storage is quite slow compared to Static RAM (SRAM), and quite energy consuming, since when reading from or writing to a DRAM chip, a whole line of a memory page is preloaded with electrical charge in order to guarantee that a subsequent read or write signal—having a quite low amplitude—reliably reads out or writes the respectively selected bits from/to the preloaded line. This operation, preparative to read or write, is called “page opening”. Immediately after the read/write, the page is mostly closed again, except in cases where before page closing it is already known or estimated that a next read or write access can be expected in near future during program run time.
Thus, within the environment of DRAM type main memory the technology of Caching has become a standard to improve read/write-throughput at random access. An overview of this cache structure is given in FIG. 1.
The usual prior art approach to avoid unnecessary page openings/closings is a cache with a cache-line for every memory page (m). Typical cache-line sizes range from 8 to 512 bytes. For every cache-line a number of tickets/tags (n) exists which is decremented for every piece of data supposed to be written to the corresponding page. When all tickets/tags are in use the associated cache-line is flushed to the memory.
This results in less page openings/closings, since the data is written ‘en-bloc’. Having a set-associative cache in this manner requires at least a (m×n) cache memory. This amount of fast memory might not be available in every hardware setup, for example in embedded systems, demanding for a different solution to improve memory access bandwidth.
Further, and with reference to FIG. 2, illustrating an address generation via a hash function resulting in a totally random memory access spanning over the whole address range in subsequent memory accesses, a conventional prior art cache as described above would require a vast amount of memory to store enough information in order to write effectively.
In U.S. Pat. No. 4,805,098 different ranks are established to store and manage write data and its address. This ranking however, consumes computing power, as it generates a lot of overhead. Further, independent of the type of computer system in use, in case of totally random access the method is not effectively operating. In particular, in embedded systems having limited computational resources only, this is a clear disadvantage.
1.3. Objectives of the Invention
The objective of the present invention is to provide an alternative method and system for operating a DRAM memory.